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Enhancement Mode MOSFET
Date:2021/10/18 21:55:31 Hits:
Want create site? Find Free WordPress Themes and plugins.Figure 1 depicts the circuit symbol and the construction of a typical n-channel enhancement-mode MOSFET. The device has four regions: the gate, the drain, the source, and the bulk. Each of these regions has its own conducting terminal. The bulk and source terminals are often electrically connected, in which case the bulk terminal is not shown in the circuit symbol. The gate consists of a conducting plate separated from the p-type bulk by a thin (10−9 m) insulating layer, usually silicon oxide SiO2. The drain and source regions are both composed of n+ material.
Figure 1 The n-channel enhancement MOSFET construction and circuit symbol
Consider the case when the gate and source terminals are connected to a reference node and the drain terminal is connected to a positive voltage supply VDD, as shown in Figure 2(a). The bulk terminal is also connected to the reference node, by virtue of its connection to the source terminal, and so the pn+ junction between the bulk and drain is reverse-biased.
Likewise, the voltage across the pn+ junction between the bulk and the source is zero, and thus that junction is also reverse-biased. Thus, a path between drain and source consists of two reverse-biased pn+ junctions such that the current from drain to source is effectively zero. In this case, the resistance from drain to source is on the order of 1012 Ω.
When the voltage from gate to source is zero, the n-channel enhancement-mode MOSFET acts as an open-circuit. Thus, enhancement-mode devices are referred to as normally off and their channels as normally open.
Suppose now that a positive DC voltage VGG is applied to the gate as shown in Figure 2(b). Positive majority charge carriers in the bulk (i.e., holes) are repelled in the region nearest the gate. At the same time, negative majority charge carriers in the source and drain (i.e., electrons) are drawn to the same region. The result is a narrow n-type channel beneath the insulating layer that separates the gate from the bulk. For a given drain voltage, the higher the gate voltage, the higher the concentration of negative charge carriers in the channel, and the higher its conductivity.
The term enhancement mode refers to the influence of the gate voltage in enhancing the conductivity of the channel. The term field effect refers to the effect of the electric field from gate to bulk that is associated with the gate voltage.
Figure 2 Channel formation in NMOS transistor: (a) With zero gate voltage, the source-bulk and bulk-drain junctions are both reverse-biased, and the channel acts as an open-circuit; (b) when a positive gate voltage is applied, positive majority carriers in the bulk (i.e., holes) are repelled by the gate leaving behind negatively charged atoms. Also, negative majority carriers from the source and drain (i.e., electrons) are drawn toward the gate. The result is a conducting n-type channel between the source and drain regions.
Depletion-mode devices also exist, in which an externally applied field depletes the channel of charge carriers by reducing the effective channel width. Depletion-mode MOSFETs are normally on (i.e., the channel is conducting) and are turned off (i.e., the channel is not conducting) by an external gate voltage.
Both enhancement- and depletion-mode MOSFETs are available with either n– or p-type channels. Enhancement-mode devices do not have a conducting channel built in; however, one can be created by the action of the gate.
On the other hand, depletion-mode devices do have a built-in conducting channel that can be depleted by the action of the gate. Depending upon the mode and channel type, FETs can be active high or active low devices, where high and low refer to the voltage of the gate relative to a common reference.
Table 1 summarizes these results. n– and p-channel MOSFETs are referred to as NMOS and PMOS transistors, respectively.
Table 1
Operating Regions and the Threshold Voltage Vt
When the gate-to-bulk voltage of an NMOS transistor (See Figure 3) is less than a threshold voltage Vt, a channel will not form between the source and drain. The result is that no current can be conducted from drain to source and the transistor is in the cutoff region. Typical values of Vt are between 0.3 and 1.0 V, although it can be significantly larger.
Figure 3 Regions of operation of NMOS transistor
When the gate-to-bulk voltage is greater than the threshold voltage Vt at any point between the source and drain, a conducting n-type channel is formed at that point. If, as usual, the source and bulk are both connected to a common reference, then the gate-to-bulk voltage is the same as the gate-to-source voltage vGS.
If the drain is also connected to the same common reference such that vDS = 0, then a channel of uniform thickness will be formed from drain to source when vGS > Vt. It is common to introduce the overdrive voltage vOV = vGS − Vt, which is the gate-to-source voltage in excess of what is necessary to create a channel. Note that vOV > 0 is another way to write vGS > Vt.
Note that if vDS = 0, then vGD≡vGS−vDS=vGSvGD≡vGS−vDS=vGS, the channel has a uniform thickness, and its resistance per unit channel length is also uniform. In this state, known as the ohmic region, the channel effectively acts as a variable resistor whose resistance is dictated by the gate voltage.
In other words, for a given value of vGS, the channel current iD is proportional to vDS. This linear relationship between iD and vDS is valid for small values of vDS.
iD∝vDSwhenvDS≪vOVOhmic Region(1)iD∝vDSwhenvDS≪vOVOhmic Region(1)
When vGS > Vt and the drain-to-source voltage vDS is no longer small but held at a positive value VDD, the channel is thinner near the drain than near the source, as depicted in Figure 2(b).
In addition, as long as vGD > Vt, the channel will still exist from source to drain. This condition is equivalent to the requirement that vDS < vOV. In this state, the channel resistance per unit length is no longer uniform, the channel current iD is proportional tov2DSvDS2, and the transistor is in the triode region.
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